Careers
PDK Engineer - Trainee
(***Not for CSE, ISE, Mech or Civil streams, or BCA, MCA, BBA, BBM etc.***)
PDK Engineer - Trainee
Pravarta's R & D team is looking for candidates who display a curiosity for scripting and automation of manual tasks, irrespective of the technical implementation involved. Problem-solving without ready references is a big part of the job, and candidates who excel at resource and time management will have an edge over others.
Role : PDK Engineer - Trainee
Qualification(s) :
B.E., B.Tech, M.Tech, B.Sc., M.Sc., in Electronics or VLSI (Not applicable to Computer, Information Science streams or other non-relevant streams such as Mechanical / Civil)
Required skill set :
C++ / Python / SKILL / SVRF or any combination of the previous set or equivalent
Linux (BASH) Shell for scripting
Basic VLSI / Electronics (Semiconductor domain) knowledge
Good verbal and / or written communication is mandatory
Differentiators :
Software / PDK Version Control (Git or equivalent)
Regression & Testing methodologies for IC Layout Designs
Prior Experience in EDA based software development preferably
Cadence or Siemens tools
Please forward your resumes with a cover letter to careers@pravartalabs.com.
Layout Engineer - Trainee
(***Not for CSE, ISE, Mech or Civil streams, or BCA, MCA, BBA, BBM etc.***)
Profile : Layout Engineer - Trainee
Pravarta's Layout team is looking for freshers or trained candidates who have a desire for continued learning and are eager to develop expertise in IC layout implementations and verification skills in collaboration with the Design & Layout Team to deliver layouts following the industry’s best practices without the need of significant rework from layout reviews.
Role : Layout Engineer - Trainee
Qualification(s) : B.E., B.Tech, M.Tech, B.Sc., M.Sc., in Electronics or VLSI Design (***Not for CS, IS, Mech or Civil streams, or BCA, MCA, BBA, BBM etc.***)
Required skill set :
Solid understanding of electronics and semiconductor physics preferably to degree level.
Strong fundamental knowledge in IC layout principles, IC reliability and failure mechanisms
Good verbal and / or written communication is mandatory
Differentiators :
Knowledge of Custom Mixed Signal Design Flows, CMOS/BCD/FINFET technologies and Device Physics
Good understanding of analog layout techniques such as floor planning, matching, latch up prevention and verification.
Exposure to the CAD tools (Virtuoso XL / ASSURA, Calibre DRC/ LVS)
Knowledge in SKILL / PERL / Python scripting is a plus.
Please forward your resumes with a cover letter to careers@pravartalabs.com.
R&D Engineer - Trainee
(***Not for CSE, ISE, Mech or Civil streams, or BCA, MCA, BBA, BBM etc.***)
R&D Engineer - Trainee
Pravarta's Research and Development (R&D) team seeks candidates who possess a genuine curiosity for scripting and automating manual tasks, regardless of the technical details involved. The role involves problem-solving without readily available references, making resource and time management skills crucial. Strong proficiency in these areas will give candidates a competitive advantage.
Role : R&D Engineer - Trainee
Qualification(s) :
B.E., B.Tech, M.Tech, B.Sc., M.Sc., in Electronics or VLSI (Not applicable to Computer, Information Science streams or other non-relevant streams such as Mechanical / Civil)
Required skill set :
Competent in C++ / Python / SKILL / SVRF or any combination of the previous set or equivalent
Linux (BASH) Shell for scripting
Good VLSI / Electronics (Semiconductor domain) knowledge
Good verbal and / or written communication is mandatory
Software / PDK Version Control (Git or equivalent)
Differentiators :
Regression & Testing methodologies for IC Layout Designs
Prior Experience in EDA based software development preferably
Cadence or Siemens tools
Please forward your resumes with a cover letter to careers@pravartalabs.com.